The present invention relates to a multi function electronic timepiece of the type which has functions such as timing, alarm, calculation, calendar, etc., more particularly, to an improved system for reducing current in a multi function electronic timepiece having a ROM-RAM (Read-Only Memory-Random Access Memory) system. Recently, multi functions in an electronic timepiece have been developed remarkably thanks to advancements in electronics, especially IC (Integrated Circuits) techniques. For example, an alarm watch, a watch with a timer or a calculator have appeared.
Thus, as the development in multi-function goes on, a problem of a limit of the number of functions comprised in the IC chip develops; especially since a rise in chip size of the IC using static C-MOS circuitry makes an increase in cost. Thus, a CPU (Central Processing Unit) system using a new circuit system including a ROM-RAM which replaces the IC using C-MOS has began to be studied and developed and is now on the market partially.
However, terminals of a ROM or RAM operate dynamically, so that a clock frequency which is sufficiently higher than that of a conventional static circuit is used. Therefore the energy consumption is great, and countermeasures have been required. Power consumption P is shown as follows: P=C.multidot.V.sup.2 .multidot.f.
As countermeasures, reduction of source voltage V, reduction of circuit driving frequency f, or reduction of stray capacitance C are considered. However, V has the limit of around 1.5 V in the case of an electronic timepiece. As for frequency f, it has also its limit because too big reduction makes the conductability drop. And stray capacity is much less hopeful because it has intimate relation with manufacturing process of the IC.
According to the present conditions mentioned above, in the case where carry is not output; a system by which a clock pulse is inhibited until a carry is output; and a system constituted so that a clock pulse is output when a switch input or base time input signal, for example, the 1/10 second signal comes and said clock pulse is stopped by an output from a program memory means; are proposed or put into practical use.
However, the countermeasurer described above are not sufficient because only an output of a timing pulse generating circuit is controlled in any case. Therefore a logic gate circuit in said timing pulse generating circuit repeats ON and OFF with a still high frequency, for example, 16KHz, 8 KHz, 4 KHz and the like.